Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
1411Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
1244For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
1394Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
1249Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
1401Post New Infosys Interview Questions
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What happens when we move a comp-3 field to an edited (say z (9). Zz-)?
What are the 4 basic layout types?
Explain why messages are immutable inside biztalk?
Is c++ or c# better?
What is filter in excel?
Will clr handle unmanaged code or not?
Is there a switch..case statement in python?
Are there any alternatives to scraping a shell and tube if a capacity increase will make the pressure drop across the exchanger too large?
How do I turn on automatic updates?
What is memo?
How do I do fill_in_the_blank for each file in a directory?
Design a reinforced concrete combined footing (rectangular) for two columns located 3.60 metres apart. The overall sizes of the columns are 40cm x 40cm and 69cm x 60cm and the loads on them are 1000 kn and 1500 kn respectively. The space available for the width of the footing is restricted to 180cm. The S.B.C. of the soil is 280 kn/mm2 use M15 concrete.
What is key lambda in python?
Explain the concept of SHAP and its role in XAI.