Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
692Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
716Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
685Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
1063You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
951What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
760For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
704Post New Infosys Interview Questions
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