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Infosys VLSI Interview Questions
Questions Answers Views Company eMail

Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

 683

Draw a 6-T SRAM Cell and explain the Read and Write operations

 793

Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

 1059

You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

 949

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

 760

Draw a CMOS Inverter. Explain its transfer characteristics

 666

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

 732

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

 704

For CMOS logic, give the various techniques you know to minimize power consumption

 848

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

 779

Draw the SRAM Write Circuitry

 649

Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

 840

Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

 809

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

 938

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

 778

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Infosys VLSI Interview Questions


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