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Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why?
- 13 Answers
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Answer / balaji kalluri
if u look at the structure of cmos-nand gate,u cud find the
parallel pmos pull-up transistor configuration whereas in
cmos-nor gate its series config,so the effective resistance
offered by 2-pmos transistors even when they r conducting
due to small Rds (drain-to-source resistance)are smaller in
comparison to the same offered by series pmos in nor
gate..hence the current delivered to the output during HIGH
o/p condition is more for nand gate,due to which it has the
ability to drive more no. of loads of similar type ,thus
offer improved FAN-OUT than cmos-nor gate.
I feel tat this could be the reason..it is true fact as per
WAKERLY text book..but there cud be 'n' no of other reasons
too..think over
thankx..
balaji kalluri
| Is This Answer Correct ? | 73 Yes | 7 No |
Answer / naseemuddin ansari
NAAND gate is more preferred than NOR because high to low
and low to high transition time is less in NAND as compared
to NOR
| Is This Answer Correct ? | 25 Yes | 3 No |
NAND is a better gate for design than NOR because at the
transistor level the mobility of electrons of NAND is
normally three times that of holes compared to NOR and thus
the NAND is a faster gate. The gate-leakage in NAND
structures is much lower. If you consider t_phl and t_plh
delays you will find that it is more symmetric in case of
NAND (the delay profile), but for NOR, one delay is much
higher than the other(obviously t_plh is higher since the
higher resistance PMOSs are in series connection which
again increases the resistance).
| Is This Answer Correct ? | 18 Yes | 6 No |
Answer / arijit banerjee
As because the logical effort of Nand gate is lower than
that of the Nor gate the time taken to drive same capacitor
with same input slew is lesser for Nand that that of Nor.
Means Nand is faster than Nor.
| Is This Answer Correct ? | 14 Yes | 4 No |
Answer / rajashekar @ nitt
nand gate is preferred because it has high driving
capacity.
| Is This Answer Correct ? | 12 Yes | 2 No |
Answer / arpan
There are many reasons for which NAND is preferred over NOR
but the most technical reason is LOGICAL EFFORT. So, lets
start with what is logical effort.
1. Logical effort :- It is defined as the ratio of the input
capacitance of the gate to the input capacitance of the
inverter, that can deliver the same output current. In other
terms we can say logical effort indicates how worse a gate
is in producing output current as compared to an inverter,
given each input of the gate has input capacitance
equivalent to an inverter. Suppose for a inverter PMOS width
is 2 and NMOS width is 1. So, here Cin = 3
NAND NOR
Cin = (n+2) Cin = (2n+1)
Cin = 4 Cin = 5
Logical Effort (g) = Cin(NAND)/Cin(Inverter)
g= 4/3 g= 5/3
So, from the above logical effort of NOR is greater than
NAND. So, NAND performs better o/p current compare to NOR.
2. In NAND PMOS is connected in parallel whereas in NOR PMOS
is connected in series, which makes the device operation slow.
| Is This Answer Correct ? | 4 Yes | 0 No |
Answer / khush
NAND is better than NOR, because in a NOR gate we have PMOS
transistors in series and when we enlarge transistor widths
gate capacitance and diffusion capacitance go up and
partially negate the benefits of widening the transistors so
very wide PMOS transistors are super capacitive. Hence we
prefer NANDs.
| Is This Answer Correct ? | 7 Yes | 4 No |
Answer / naqash
NAAND gate is more preferred than NOR because high to low
and low to high transition time is less in NAND as compared
to NOR and it has high driving capacity thats why it is preffered.
| Is This Answer Correct ? | 4 Yes | 1 No |
Answer / aaditya prakash
CMOS NAND GATE is preferred to CMOS NOR GATE because in Pull Down Network (generally used because of easy comparison with ground potential) is in series configuration offers less Resistance(drain to source. Thus. more current is obtained at the output.
| Is This Answer Correct ? | 1 Yes | 0 No |
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