VLSI Interview Questions
Questions Answers Views Company eMail

what is conductance and valence band?

1 3954

What is Fermi level?

5 5598

How does Vbe and Ic change with temperature?

Qualcomm,

2100




If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?

1 1948

what is Channel length modulation?

Intel,

2 2577

what is the doping?

5 4015

How does a pn junction works?

Wipro,

2 4292

What is the depletion region?

1 3500




Tell me the parameters as many as possible you know that used to character an amplifier?

1 1233

What are the two types of noise of MOSFET, how to eliminate them?(Thermal and Flicker).

Analog Devices,

4 9571

What is the build-in potential?

Wipro,

1130

Tell me how MOSFET works.

1255

For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?

2 8263

How does a Bandgap Voltage reference work?

2326

What is the ideal input and output resistance of a current source?

1821


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Un-Answered Questions { VLSI }

If not into production, how far did you follow the design and why did not you see it into production?

1004


Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

334


Are you familiar with the term MESI?

1377


What are the main issues associated with multiprocessor caches and how might you solve them?

1014


What is the build-in potential?

1130






How to improve these parameters? (Cascode topology, use long channel transistors)

1042


What types of high speed CMOS circuits have you designed?

1400


Are you familiar with the term snooping?

2228


What is the critical path in a SRAM?

1886


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

2707


Basic Stuff related to Perl?

1678


What is Noise Margin? Explain the procedure to determine Noise Margin?

1246


Explain sizing of the inverter?

3005


Explain how MOSFET works?

2100


Explain the operation of a 6T-SRAM cell?

3242