what is conductance and valence band?1 3106
What is Fermi level?5 4548
How does Vbe and Ic change with temperature?1707
If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?1125
what is the doping?5 3052
What is the depletion region?1 2877
What are the two types of noise of MOSFET, how to eliminate them?(Thermal and Flicker).4 8408
What is the build-in potential?860
For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?2 6491
What is pipelining and how can we increase throughput using pipelining?
What happens if we delay the enabling of Clock signal?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
Describe the various effects of scaling?
Explain the working of 4-bit Up/down Counter?
How to improve these parameters? (Cascode topology, use long channel transistors)
Insights of a 2 input NOR gate. Explain the working?
Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
If not into production, how far did you follow the design and why did not you see it into production?
What types of high speed CMOS circuits have you designed?
What types of CMOS memories have you designed? What were their size? Speed?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
What's the price in 1K quantity?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
What was your role in the silicon evaluation or product ramp? What tools did you use?