If not into production, how far did you follow the design and why did not you see it into production?

1030

Explain the Charge Sharing problem while sampling data from a Bus?

1170

Are you familiar with the term MESI?

1403

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

2081

What is Noise Margin? Explain the procedure to determine Noise Margin?

1274

How do you size NMOS and PMOS transistors to increase the threshold voltage?

1708

How to improve these parameters? (Cascode topology, use long channel transistors)

1065

What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

1336

What types of CMOS memories have you designed? What were their size? Speed?

1902

What happens if we use an Inverter instead of the Differential Sense Amplifier?

1892

Explain CMOS Inverter transfer characteristics?

2642

What transistor level design tools are you proficient with? What types of designs were they used on?

3763

How can you model a SRAM at RTL Level?

4238

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

364

Write a VLSI program that implements a toll booth controller?

2836