In a processor these are 120 instructions . Bits needed to impliment this instructions [a] 6 [b] 7 [c] 10 [d] none2 8390
In 8085 microprocessor READY signal does.which of the following is incorrect statements [a]It is input to the microprocessor [b] It sequences the instructions2 7955
load a mul a store t1 load b mul b store t2 mul t2 add t1 then the content in accumulator is2 5891
In 8085 microprocessor READY signal does.which of the following is incorrect statements [a]It is input to the microprocessor [b] It sequences the instructions4 7356
what is conductance and valence band?1 4050
What is Fermi level?5 5721
How does Vbe and Ic change with temperature?2179
If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?1 2020
what is the doping?5 4108
What is the depletion region?1 3547
Tell me the parameters as many as possible you know that used to character an amplifier?1 1282
If not into production, how far did you follow the design and why did not you see it into production?
Explain the Charge Sharing problem while sampling data from a Bus?
Are you familiar with the term MESI?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
What is Noise Margin? Explain the procedure to determine Noise Margin?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
How to improve these parameters? (Cascode topology, use long channel transistors)
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
What types of CMOS memories have you designed? What were their size? Speed?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
Explain CMOS Inverter transfer characteristics?
What transistor level design tools are you proficient with? What types of designs were they used on?
How can you model a SRAM at RTL Level?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
Write a VLSI program that implements a toll booth controller?