Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
No Answer is Posted For this Question
Be the First to Post Answer
Explain the sizing of the inverter?
What are the different limitations in increasing the power supply to reduce delay?
What is setup time and hold time?
How do you detect if two 8-bit signals are same?
what is charge sharing?
What is Body Effect?
0 Answers CG CoreEL, Cisco, TA,
What transistor level design tools are you proficient with? What types of designs were they used on?
What was your role in the silicon evaluation or product ramp? What tools did you use?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
For CMOS logic, give the various techniques you know to minimize power consumption
Explain Cross section of an NMOS transistor?