Have you studied buses? What types?

1 Answers   Intel,

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What happens if we delay the enabling of Clock signal?

0 Answers  

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Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  

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What happens if we use an Inverter instead of the Differential Sense Amplifier?

0 Answers  

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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How does Vbe and Ic change with temperature?

0 Answers   Qualcomm,

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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what is short Channel effect.

2 Answers  

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Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

0 Answers   Infosys,

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

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What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

0 Answers   Intel,

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Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,

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