Answer / narendra

issue : Cache coherency or Data coherency. The problem is
all the processors cache should have exactly the same
shared data (cohenrent data). and there are races possible
with multiprocessors.

possible solution: use one central cache controller which
will get all the read/write requests from all the
processors and peripherals so that it can make sure there
are no races and cache coherency is maintained.

How does Vbe and Ic change with temperature?

0 Answers   Qualcomm,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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What are the different design constraints occur in the synthesis phase?

0 Answers  

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What is Body Effect?

0 Answers   CG CoreEL, Cisco, TA,

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What types of high speed CMOS circuits have you designed?

2 Answers   Infosys, Intel,

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Tell me how BJT works.

2 Answers  

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Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

0 Answers   Infosys,

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Give various factors on which threshold voltage depends.

0 Answers  

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Mention what are the different gates where Boolean logic are applicable?

0 Answers  

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If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?

1 Answers  

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what is the difference between the TTL chips and CMOS chips?

0 Answers  

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Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

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