Interested to Buy Any Domain ? << Click Here >> for more details...
Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why?
- 13 Answers
- 37457 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / sarang
NAND is a better gate for design than NOR because at the
transistor level the mobility of electrons of NAND is
normally three times that of holes compared to NOR and thus
the NAND is a faster gate. The gate-leakage in NAND
structures is much lower. If you consider t_phl and t_plh
delays you will find that it is more symmetric in case of
NAND (the delay profile), but for NOR, one delay is much
higher than the other(obviously t_plh is higher since the
higher resistance PMOSs are in series connection which
again increases the resistance).
| Is This Answer Correct ? | 18 Yes | 6 No |
Post New Answer View All Answers
Implement a 2 I/P and gate using Tran gates?
What is the critical path in a SRAM?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
Mention what are the different gates where Boolean logic are applicable?
What is the difference between the mealy and moore state machine?
Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
What types of high speed CMOS circuits have you designed?
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
Explain the working of Insights of a pass gate ?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
Explain about 6-T XOR gate?
