Interested to Buy Any Domain ? << Click Here >> for more details...
Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why?
- 13 Answers
- 37025 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / sarang
NAND is a better gate for design than NOR because at the
transistor level the mobility of electrons of NAND is
normally three times that of holes compared to NOR and thus
the NAND is a faster gate. The gate-leakage in NAND
structures is much lower. If you consider t_phl and t_plh
delays you will find that it is more symmetric in case of
NAND (the delay profile), but for NOR, one delay is much
higher than the other(obviously t_plh is higher since the
higher resistance PMOSs are in series connection which
again increases the resistance).
| Is This Answer Correct ? | 18 Yes | 6 No |
Post New Answer View All Answers
What is the critical path in a SRAM?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What are the steps involved in preventing the metastability?
What was your role in the silicon evaluation/product ramp? What tools did you use?
What is the function of enhancement mode transistor?
Draw a 6-T SRAM Cell and explain the Read and Write operations
How can you model a SRAM at RTL Level?
Draw a CMOS Inverter. Explain its transfer characteristics
Explain the Various steps in Synthesis?
Design an 8 is to 3 encoder using 4 is to encoder?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
What is the main function of metastability in vsdl?
Are you familiar with the term snooping?
Explain what is Verilog?
Implement a 2 I/P and gate using Tran gates?
