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Differences between D-Latch and D flip-flop?
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Answer / sanjiv
latch is lever dependent and flipflop are edge dependent
| Is This Answer Correct ? | 25 Yes | 17 No |
Answer / gou9864
ANS 2 latch can have clock but there will be no diff with or with out clock as the latch is level sensitive.
We can use two latches to make a flip flop by assigning a edge sensitive clk using Master slave configuration
| Is This Answer Correct ? | 2 Yes | 0 No |
Answer / alena khan
a flip flop consist of two latches (positive and negative
level sensitive latchs). .
| Is This Answer Correct ? | 2 Yes | 0 No |
Answer / guru sai prasad reddy.m
Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of
information. The main difference between latches and flip-flops is that for latches, their outputs are constantly
affected by their inputs as long as the enable signal is asserted. In other words, when they are enabled, their content
changes immediately when their inputs change. Flip-flops, on the other hand, have their content change only either
at the rising or falling edge of the enable signal. This enable signal is usually the controlling clock signal. After the
rising or falling edge of the clock, the flip-flop content remains constant even if the input changes.
| Is This Answer Correct ? | 2 Yes | 0 No |
Answer / neha
D latch is sensitive to the clock transition either high to low or vice versa.i.e. output responds to the change in input during clock transition , after that it maintains its state.
D flip flop is sensitive to the pulse duration. i.e. output tracks input during entire pulse width(1 or 0).
| Is This Answer Correct ? | 1 Yes | 1 No |
Answer / shashwat rohilla
The main difference is D-Latch does not have a clock but D-
Flip Flop does.
A Latch with the facility of the clock is a Flip Flop.
As far as Level-Triggering is concerned, a FF can also be
level-triggered. It is converted to edge triggered mode by
using 2 FF (Master Slave).
http://en.wikipedia.org/wiki/Flip-flop_(electronics)
| Is This Answer Correct ? | 0 Yes | 1 No |
Answer / seokchai
latch does not have clock while flip-flop does
| Is This Answer Correct ? | 118 Yes | 204 No |
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
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