Interested to Buy Any Domain ? << Click Here >> for more details...
Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock
signal? (You can't resize the combinational circuit
transistors)
- 6 Answers
- 13756 Views
- I also Faced
- E-Mail Answers
Answers were Sorted based on User's Feedback
Answer / adi
Insert a small buffer to increase the skew between the two
regs. This can be quick fix only in some cases though
| Is This Answer Correct ? | 13 Yes | 0 No |
Answer / pavankumar v vijapur
use register retiming concept .......
i.e split up comb delay in two paths using a flop
| Is This Answer Correct ? | 4 Yes | 1 No |
Answer / ram
when there is a combo delay which is more than the clock
time period, though all the above can be a solution if the
delay is small, normally they mark it as a multi clock cycle
path.
| Is This Answer Correct ? | 3 Yes | 1 No |
Answer / guest
Ideally, clock period will be increased (reducing maximum
operation frequency)
| Is This Answer Correct ? | 3 Yes | 3 No |
What types of high speed CMOS circuits have you designed?
Why do we use a Clock tree?
Differences between Array and Booth Multipliers?
What is a D-latch? Write the VHDL Code for it?
What are the different ways in which antenna violation can be prevented?
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
what are three regions of operation of MOSFET and how are they used?
what is short Channel effect.
How do you detect a sequence of "1101" arriving serially from a signal line?
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
Insights of a Tri-state inverter?
Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;
86 Family 
