Why do we need both PMOS and NMOS transistors to implement a pass gate?

3 Answers   INEL, Intel,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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Explain what is slack?

0 Answers  

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What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

0 Answers   Intel,

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What is the depletion region?

1 Answers  

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Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?

6 Answers   Intel,

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Define threshold voltage?

32 Answers   College School Exams Tests, Intel, JHG, Wipro,

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Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

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Describe the various effects of scaling?

0 Answers   Infosys,

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If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

0 Answers   Intel,

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Explain the working of Insights of an inverter ?

0 Answers   Intel,

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Explain how Verilog is different to normal programming language?

0 Answers  

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