Explain the various MOSFET Capacitances & their significance?

1 Answers  

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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

0 Answers   Infosys,

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What was your role in the silicon evaluation or product ramp? What tools did you use?

0 Answers   Intel,

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Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,

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verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.

2 Answers   Cosmic Circuits, HP,

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How can you model a SRAM at RTL Level?

0 Answers   Infosys,

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Explain various adders and difference between them?

0 Answers   Intel,

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If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?

1 Answers  

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What is LVS, DRC?

10 Answers   IBM, Intel,

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What is the build-in potential?

1 Answers   Wipro,

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What are the different limitations in increasing the power supply to reduce delay?

2 Answers  

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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

0 Answers   Infosys,

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