VLSI Interview Questions, Answers for Freshers and Experienced asked in various Company Job Interviews

VLSI Interview Questions

Questions Answers Views Company eMail

6-T XOR gate?

Intel,

4250

Differences between blocking and Non-blocking statements in Verilog?

Intel,

5 21023

Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

IIT, Intel,

1 20809

Differences between functions and Procedures in VHDL?

Intel,

5 54973

What is component binding?

Intel,

2 6296

What is polymorphism? (C++)

Intel,

2 6070

What is hot electron effect?

Intel,

3 13363

Define threshold voltage?

College School Exams Tests, Intel, JHG, Wipro,

32 135168

Factors affecting Power Consumption on a chip?

Intel,

7 17342

Explain Clock Skew?

Intel, nvidia,

6 21609

Why do we use a Clock tree?

Intel,

3 13418

Explain the various Capacitances associated with a transistor and which one of them is the most prominent?

Intel,

2 8182

Explain the Various steps in Synthesis?

Intel,

3281

Explain ASIC Design Flow?

Intel, JK Associates, Mind Tree,

2 15427

Explain Custom Design Flow?

Intel,

2 7084

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Un-Answered Questions { VLSI }

What types of high speed CMOS circuits have you designed?

2576

Explain what is multiplexer?

1082

Explain the Working of a 2-stage OPAMP?

1198

Explain the Charge Sharing problem while sampling data from a Bus?

4732

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

1458

Explain what is scr (silicon controlled rectifier)?

1064

Cross section of a PMOS transistor?

4773

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1455

6-T XOR gate?

4250

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

1338

What are the changes that are provided to meet design power targets?

1122

What is the difference between the mealy and moore state machine?

1121

What are the steps involved in designing an optimal pad ring?

1172

In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

4126

What is Noise Margin? Explain the procedure to determine Noise Margin?

2458

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