Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
1052You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
942What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
757For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
702Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
834Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
807For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
935Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
774Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
859
Explain the Various steps in Synthesis?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
Explain what is multiplexer?
Explain the operation of a 6T-SRAM cell?
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
What are the different gates where boolean logic are applicable?
What is the function of enhancement mode transistor?
Basic Stuff related to Perl?
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
Explain CMOS Inverter transfer characteristics?
What are the different design constraints occur in the synthesis phase?
What types of CMOS memories have you designed? What were their size? Speed?
What types of high speed CMOS circuits have you designed?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
Insights of a 4bit adder/Sub Circuit?
