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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
1586You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
1504What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
1243How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
1169For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
1224Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
1408Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
1238For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
1390Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
1246Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
1397
Differences between IRSIM and SPICE?
Are you familiar with the term MESI?
What are the steps involved in designing an optimal pad ring?
Explain the operation considering a two processor computer system with a cache for each processor.
What are the main issues associated with multiprocessor caches and how might you solve them?
Draw the SRAM Write Circuitry
What types of CMOS memories have you designed? What were their size? Speed?
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
Give the cross-sectional diagram of the cmos.
What are the different design constraints occur in the synthesis phase?
Draw the Layout of an Inverter?
What's the price in 1K quantity?
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
How can you construct both PMOS and NMOS on a single substrate?
what is the use of defpararm?
