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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
1603You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
1517What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
1268How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
1183For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
1239Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
1416Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
1250For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
1404Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
1257Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
1409
Write a program to explain the comparator?
What is the function of chain reordering?
Explain what is slack?
Explain what is the use of defpararm?
What was your role in the silicon evaluation or product ramp? What tools did you use?
What transistor level design tools are you proficient with? What types of designs were they used on?
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
Give the cross-sectional diagram of the cmos.
what are three regions of operation of MOSFET and how are they used?
What are the different design techniques required to create a layout for digital circuits?
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
Mention what are the two types of procedural blocks in Verilog?
Mention what are the different gates where Boolean logic are applicable?
Explain various adders and difference between them?
Write a VLSI program that implements a toll booth controller?
