Why do we use a Clock tree?
Answers were Sorted based on User's Feedback
Answer / sharekhan
Clock tree is usd for equal distribution of clock in a VLSI
circuitry.In this technique the VLSI blocks are at equal
distance from the central clock.This technique is ues to
eliminate skew problem.
Arrangemnet is in the form of alphabhet "H" with VLSI
blocks are arranged at the end of the alphabhet H and clock
circuitry aplied at the centre of the "H".THus each block
is at equal distance from the clock circuitry.
| Is This Answer Correct ? | 18 Yes | 0 No |
Answer / arghya sasmal
During CTS our goal is to
1) minimize the clock skew
2)minimize the clock tree power dissipation
In CTS buffers and inverters are placed in clock net to minimize the skew.
Clock nets are optimized and their driving cells are supposed to match RC values and impedance ...and minimize the clock tree power dissipation
| Is This Answer Correct ? | 4 Yes | 0 No |
Answer / purna
The main goals of CTS are
1. Clock signal is propagate to all flops in same time.
2. Low global and local skew.
3. Less insertion delay.
4. For low power designs Clock gating cells are added based
on the designer requirement.
5.Selecting a tree structure from (H,Y,binary and fish bone
etc...)
6. less number of buffer and inverters in the clock path.
7. Clock pin has high fanout to balance skew, we need to
synthesis the clock path separately.
| Is This Answer Correct ? | 3 Yes | 0 No |
What is latchup? Explain the methods used to prevent it?
What is Body Effect?
0 Answers CG CoreEL, Cisco, TA,
Insights of a 4bit adder/Sub Circuit?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What is the ideal input and output resistance of a current source?
Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
What are the steps required to solve setup and hold violations in vlsi?
What is Noise Margin? Explain the procedure to determine Noise Margin?
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
what is the difference between the testing and verification?