Answers were Sorted based on User's Feedback
Answer / sharekhan
Clock tree is usd for equal distribution of clock in a VLSI
circuitry.In this technique the VLSI blocks are at equal
distance from the central clock.This technique is ues to
eliminate skew problem.
Arrangemnet is in the form of alphabhet "H" with VLSI
blocks are arranged at the end of the alphabhet H and clock
circuitry aplied at the centre of the "H".THus each block
is at equal distance from the clock circuitry.
|Is This Answer Correct ?||18 Yes||0 No|
Answer / arghya sasmal
During CTS our goal is to
1) minimize the clock skew
2)minimize the clock tree power dissipation
In CTS buffers and inverters are placed in clock net to minimize the skew.
Clock nets are optimized and their driving cells are supposed to match RC values and impedance ...and minimize the clock tree power dissipation
|Is This Answer Correct ?||4 Yes||0 No|
Answer / purna
The main goals of CTS are
1. Clock signal is propagate to all flops in same time.
2. Low global and local skew.
3. Less insertion delay.
4. For low power designs Clock gating cells are added based
on the designer requirement.
5.Selecting a tree structure from (H,Y,binary and fish bone
6. less number of buffer and inverters in the clock path.
7. Clock pin has high fanout to balance skew, we need to
synthesis the clock path separately.
|Is This Answer Correct ?||3 Yes||0 No|
Insights of a 4bit adder/Sub Circuit?
What was your role in the silicon evaluation or product ramp? What tools did you use?
Define threshold voltage?
Explain Basic Stuff related to Perl?
Explain Custom Design Flow?
What is hot electron effect?
Tell me the parameters as many as possible you know that used to character an amplifier?
what is the use of defpararm?
Write a program to explain the comparator?
what is charge sharing?
What is polymorphism? (C++)
What is charge sharing?