6-T XOR gate?
Implement a 2 I/P and gate using Tran gates?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
What are the different types of skews used in vlsi?
Explain CMOS Inverter transfer characteristics?
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
Design an 8 is to 3 encoder using 4 is to encoder?
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
How can you construct both PMOS and NMOS on a single substrate?
How about voltage source?
Explain sizing of the inverter?
Explain Cross section of a PMOS transistor?
Explain the Various steps in Synthesis?
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?