Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

3089

Write a program to explain the comparator?

1098

Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

1093

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

2845

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1409

Explain what is the depletion region?

1037

You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

2632

What are the changes that are provided to meet design power targets?

1065

In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

1159

What transistor level design tools are you proficient with? What types of designs were they used on?

3397

Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

1416

Describe the various effects of scaling?

4749

Mention what are the two types of procedural blocks in Verilog?

1232

Implement a 2 I/P and gate using Tran gates?

3983

what is verilog?

1071