What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

3209

Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

1408

What was your role in the silicon evaluation or product ramp? What tools did you use?

2258

Explain Cross section of a PMOS transistor?

1165

Explain CMOS Inverter transfer characteristics?

3864

For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

2348

What transistor level design tools are you proficient with? What types of designs were they used on?

3388

Mention what are the different gates where Boolean logic are applicable?

1057

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1397

What types of CMOS memories have you designed? What were their size? Speed?

4605

You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

1504

Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

2272

what is a sequential circuit?

1088

Explain the operation considering a two processor computer system with a cache for each processor.

2807

Explain about 6-T XOR gate?

1179