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Differences between blocking and Non-blocking statements in
Verilog?

Answers were Sorted based on User's Feedback

Differences between blocking and Non-blocking statements in Verilog?..

cp mistake in 1st one.
-----------------------------------

Blocking statements are executed on after another
represented by '='

Ex. lets take two variables
reg A:0;
reg B:1;
initial
begin
A = B;
B = A;
end

Ans
A = 1
B = 1

Non Blocking
instructions are executed concurrently
represented by '<='

Ex. lets take two variables
reg A:0;
reg B:1;
initial
begin
A <= B;
B <= A;
end

Ans
A = 1
B = 0

 Is This Answer Correct ? 66 Yes 1 No

Differences between blocking and Non-blocking statements in Verilog?..

@ Remya,

With non-blocking statements as shown above, A will always
get the OLD/previous value of B, and B will always get the
OLD/previous value of A.

Because, in a non-blocking statement assignment, the right
hand side of the statement gets evaluated right away, but
doesn't get assigned to the left hand side of the statement
until at the end of the time step.

 Is This Answer Correct ? 20 Yes 1 No

Differences between blocking and Non-blocking statements in Verilog?..

Blocking statements are executed on after another
represented by '='

Ex. lets take two variables
reg A:0;
reg B:1;
initial
begin
A = B;
B = A;
end

Ans
A = 1
B = 1

Non Blocking
instructions are executed concurrently
represented by '=>'

Ex. lets take two variables
reg A:0;
reg B:1;
initial
begin
A = B;
B = A;
end

Ans
A = 1
B = 0

 Is This Answer Correct ? 35 Yes 18 No

Differences between blocking and Non-blocking statements in Verilog?..

DURING BLOCKING STATEMENTS, PREVIOUS VALUES GETS STORED TO
THE LHS.

WHERE AS IN NON BLOCKING STATEMENT, SINCE IT IS EXECUTING IN
PARALLEL 1ST SIMULATOR READS AND STORES IN TEMPORARY
REGISTER INTERNALLY IN SIMULATOR. THEN AT THE END OF THE
TIME UNIT IT IS ASSIGNED TO THE LHS.

ANYWAYS FROM MY POINT OF VIEW A OR B DONT GET THE PREV/OLD
VALUE

 Is This Answer Correct ? 7 Yes 2 No

Differences between blocking and Non-blocking statements in Verilog?..

Yes,the explanation is ok but after a particular time
units,the value of B must be equal to 1 no?

 Is This Answer Correct ? 6 Yes 9 No

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