What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
4 6891Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
13 33389
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
What's the price in 1K quantity?
What are the steps required to solve setup and hold violations in vlsi?
Explain the working of 4-bit Up/down Counter?
Write a VLSI program that implements a toll booth controller?
Draw the stick diagram of a NOR gate. Optimize it
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
Explain what is the depletion region?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
Explain how Verilog is different to normal programming language?
Explain the working of Insights of an inverter ?
What is the critical path in a SRAM?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
Are you familiar with the term MESI?
Explain what is Verilog?
