Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

3146

Explain Cross section of a PMOS transistor?

1234

For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

1257

What does the above code synthesize to?

2607

What is the difference between nmos and pmos technologies?

1115

Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

2337

What is Body Effect?

2521

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

3267

What's the price in 1K quantity?

2826

Explain Basic Stuff related to Perl?

1047

Why does the present vlsi circuits use mosfets instead of bjts?

1299

what is multiplexer?

1166

Explain why is the number of gate inputs to cmos gates usually limited to four?

1508

what are three regions of operation of MOSFET and how are they used?

1242

Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3869