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Factors affecting Power Consumption on a chip?
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Answer / srujana
Power consumption on a chip can be classified majorly in
to 2 types:
1. Static Power consumption
2. Dynamic Power consumption
Static Power consumption: Leakage power is the major
contributor in static power consumption. The subthreshold
leakage power due to reduced threshold value due to
reduced supply voltages as technology is shrinking is the
major contributor of leakage power.
Dynamic Power consumption:
1.This is due to the increase in frequency of the chip,
which results in high switching rates of the clock
2. Due to increase in the complexity of the chip and the
increase in the instance count of the chip.
| Is This Answer Correct ? | 16 Yes | 0 No |
Answer / khush
the faster the clock the more power used, the longer the
wires the more power used, the number of transitions i.e.
the faster the switching the more power used - power is
proportional to switching frequency.
| Is This Answer Correct ? | 8 Yes | 0 No |
Answer / pankaj
power is dirlectly proportional to the square of suplly
voltage so is the supply voltage reduces the power is also
reduced but the lekage cuurent is increased. so voltage
level can't be reduced so much.
| Is This Answer Correct ? | 6 Yes | 1 No |
Answer / subu
1) Number of state Transition.
2) Ideal clock input (instead we can give clock gating)
| Is This Answer Correct ? | 5 Yes | 2 No |
Answer / bhawna
In addition to Static and Dynamic Power the other major contributor is:
Activity factor - how often the gates are switching
Optimal sizing - same logical effort is approximately same delay however the least size will give least power
Total Capacitance charging/discharging per cycle - depends on optimal layout design to reduce the capacitance by proper choice of available metal layers
| Is This Answer Correct ? | 2 Yes | 0 No |
Answer / rajkumar
Leakage power
Dynamic power
Short circuit power
| Is This Answer Correct ? | 0 Yes | 0 No |
Answer / p.mgr
If the coding of chip is increased then the power
consumption also increased
| Is This Answer Correct ? | 4 Yes | 14 No |
How do you detect a sequence of "1101" arriving serially from a signal line?
Explain the working of Insights of a pass gate ?
Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;
For CMOS logic, give the various techniques you know to minimize power consumption
What was your role in the silicon evaluation or product ramp? What tools did you use?
What are the different limitations in increasing the power supply to reduce delay?
what is the difference between the testing and verification?
What happens if we increase the number of contacts or via from one metal layer to the next?
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
What is the difference between the mealy and moore state machine?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
What is setup time and hold time?
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