Answer / amar

ASIC design flow:
Stands for Application specific integrated circuit.

This kind of design flow has been completely automated
with few manual steps

Below is the flow

1 ] system level specification
2 ]RTL coding and simulation

2 ] netlist synthesis , dft scan insertion ---> DFT ATPG,
STA,GLS can be run in this stage

3 ] physical design process
netlist extraction with actual parasitics
sign off STA , GLS , Power analysis will be done here

GDS2 ----> Manufacturer

In ASIC , We use standard cells which are predesigned and
pre verified cells created as library from where physical
design tools will choose the correct cell to place and route.

Comapre and contrast this with Custom IC design where we do
not have so much automation , and also we do not use
standard cells instead custom cells are created for use in
custom IC design

Answer / david schkolnik

To Answer #1 I must add the check done between steps:
After:
architecture is defined: Review with peers:
RTL coding: Logic simulation with tools like NCsim
Synthesis: first shot STA of (with estimated delays).
Formal verification against RTL (w/Formality)
DFT insertion and ATPG: Logic simulation, coverage, - Formal verification against
pre-DFT netlist.
Place and Route: sign-off STA (with actual delays)
LVS, DRC

Because the Verification process of the original code continues in parallel during the rest of the project, some bugs come up very late when it's too late to re-do the whole thing. Sometimes timing problems need late fixes. These small changes are called ECO, which are made straight on Layout. Then LVS needs to be run again and the result be analyzed by the top engineers in the team. Still, many bugs are born in this stage.

How can you model a SRAM at RTL Level?

1 Answers  

---

Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

---

Cross section of an NMOS transistor?

3 Answers   Intel,

---

What is look up table in vlsi?

0 Answers  

---

Are you familiar with the term MESI?

0 Answers   Intel,

---

What is Fermi level?

5 Answers  

---

What are the Factors affecting Power Consumption on a chip?

0 Answers   Intel,

---

Write a VLSI program that implements a toll booth controller?

0 Answers   Patni,

---

What is the difference between synchronous and asynchronous reset?

0 Answers  

---

What are the Advantages and disadvantages of Mealy and Moore?

0 Answers   Intel,

---

Are you familiar with VHDL and/or Verilog?

1 Answers   Intel,

---

What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

---