Answer / seetharamukg

Signals updates a value after some "delta" time or at the
end of the process. But variable updates a value immediately.

Both variable and signals are synthesizable.
Designer should know hoe to use these 2 objects.

Ex: Signal usage
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor_sig is
port (
A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC
);
end xor_sig;
architecture SIG_ARCH of xor_sig is
signal D: STD_LOGIC;
begin
SIG:process (A,B,C)
begin
D <= A; -- ignored !!
X <= C xor D;
D <= B; -- overrides !!
Y <= C xor D;
end process;
end SIG_ARCH;

Variable usage:
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity xor_var is
port (
A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC
);
end xor_var;
architecture VAR_ARCH of xor_var is
begin
VAR:process (A,B,C)
variable D: STD_LOGIC;
begin
D := A;
X <= C xor D;
D := B;
Y <= C xor D;
end process;
end VAR_ARCH;

Explain why present VLSI circuits use MOSFETs instead of BJTs?

0 Answers  

---

Insights of a 2 input NOR gate. Explain the working?

1 Answers   Infosys, Intel,

---

Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

---

What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?

4 Answers   Intel,

---

For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

3 Answers   Intel,

---

Explain the Working of a 2-stage OPAMP?

0 Answers   Intel,

---

Explain the working of 4-bit Up/down Counter?

0 Answers   Intel,

---

what is SCR (Silicon Controlled Rectifier)?

0 Answers  

---

Implement a function with both ratioed and domino logic and merits and demerits of each logic?

0 Answers   Intel,

---

what is body effect?

1 Answers  

---

What is the function of enhancement mode transistor?

0 Answers  

---

How do you size NMOS and PMOS transistors to increase the threshold voltage?

4 Answers  

---