Answer / sham

w r t VHDL component binding is binding of an entity with an architecture declared else where..

Answer / khush

If an entity contains many architectures and any one of
the possible architecture binding with its entity is done
using configuration. It is used to bind the architecture
body to its entity and a component with an entity.

Syntax:

configuration configuration_name of entity_name is
block_configuration;
end configuration_name.

Block_configuration defines the binding of components in a
block. This can be written as

for block_name
component_binding;
end for;
block_name is the name of the architecture body. Component
binding binds the components of the block to entities. This
can be written as,

for component_labels:component_name
block_configuration;
end for;

Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?

6 Answers   Intel,

---

What products have you designed which have entered high volume production?

1 Answers   Intel,

---

How do you size NMOS and PMOS transistors to increase the threshold voltage?

1 Answers   Infosys,

---

What is pipelining and how can we increase throughput using pipelining?

1 Answers   Intel,

---

what is the difference between the TTL chips and CMOS chips?

1 Answers  

---

Why does the present vlsi circuits use mosfets instead of bjts?

1 Answers  

---

Mention what are three regions of operation of mosfet and how are they used?

1 Answers  

---

Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,

---

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

1 Answers   Infosys,

---

Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

1 Answers  

---

What are the different measures that are required to achieve the design for better yield?

1 Answers  

---

Explain the Charge Sharing problem while sampling data from a Bus?

1 Answers  

---