VLSI Interview Questions, Answers for Freshers and Experienced asked in various Company Job Interviews

VLSI Interview Questions

Questions Answers Views Company eMail

How can you construct both PMOS and NMOS on a single substrate?

IBM, Intel,

4930

What happens when the gate oxide is very thin?

Intel,

3 13913

What is setup time and hold time?

Intel,

1 6200

Write a pseudo code for sorting the numbers in an array?

Intel,

2 14708

What is pipelining and how can we increase throughput using pipelining?

Intel,

1 5109

Explain about stuck at fault models, scan design, BIST and IDDQ testing?

Intel,

3 13202

What is SPICE?

Intel,

4 17502

Differences between IRSIM and SPICE?

Intel,

5386

Differences between netlist of HSPICE and Spectre?

Intel,

1 8866

What is FPGA?

Intel,

7 14568

Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

Intel,

3329

Draw the Layout of an Inverter?

Intel,

2442

If the current thru the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

Intel,

1 6934

Implement F = AB+C using CMOS gates?

Intel,

2 11316

Working of a 2-stage OPAMP?

Intel, Tata Elxsi,

3120

Post New VLSI Questions

Un-Answered Questions { VLSI }

Draw the SRAM Write Circuitry

1137

Explain Cross section of a PMOS transistor?

1165

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

1169

How do you size NMOS and PMOS transistors to increase the threshold voltage?

2967

What is Noise Margin? Explain the procedure to determine Noise Margin?

2412

what is multiplexer?

1097

Explain what is scr (silicon controlled rectifier)?

1017

What is the main function of metastability in vsdl?

1005

How logical gates are controlled by boolean logic?

1019

Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3820

What is the function of chain reordering?

1011

What are the different gates where boolean logic are applicable?

995

How can you model a SRAM at RTL Level?

5683

Explain depletion region.

977

In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

1126

For More Un-Answered { VLSI } Questions Click Here