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VLSI Interview Questions
Questions Answers Views Company eMail

How can you construct both PMOS and NMOS on a single substrate?

IBM, Intel,

3801

What happens when the gate oxide is very thin?

Intel,

3 11247

What is setup time and hold time?

Intel,

1 4774

Write a pseudo code for sorting the numbers in an array?

Intel,

2 12925

What is pipelining and how can we increase throughput using pipelining?

Intel,

1 3590

Explain about stuck at fault models, scan design, BIST and IDDQ testing?

Intel,

3 10213

What is SPICE?

Intel,

4 13448

Differences between IRSIM and SPICE?

Intel,

4294

Differences between netlist of HSPICE and Spectre?

Intel,

1 7202

What is FPGA?

Intel,

7 10530

Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

Intel,

2439

Draw the Layout of an Inverter?

Intel,

1603

If the current thru the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

Intel,

1 5219

Implement F = AB+C using CMOS gates?

Intel,

2 9028

Working of a 2-stage OPAMP?

Intel, Tata Elxsi,

2160


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Un-Answered Questions { VLSI }

Explain about 6-T XOR gate?

237


Implement a function with both ratioes and domino logic and merits and demerits of each logic?

216


What are the different ways in which antenna violation can be prevented?

228


What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

268


How about voltage source?

1401






Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

215


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3011


Draw a 6-T SRAM Cell and explain the Read and Write operations

244


What are the main issues associated with multiprocessor caches and how might you solve them?

1314


Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

253


What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

1594


Insights of a 4bit adder/Sub Circuit?

2415


What's the price in 1K quantity?

1953


Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

1834


Explain sizing of the inverter?

3322