VLSI Interview Questions
Questions Answers Views Company eMail

How can you construct both PMOS and NMOS on a single substrate?

IBM, Intel,

4473

What happens when the gate oxide is very thin?

Intel,

3 12658

What is setup time and hold time?

Intel,

1 5421

Write a pseudo code for sorting the numbers in an array?

Intel,

2 13729

What is pipelining and how can we increase throughput using pipelining?

Intel,

1 4338

Explain about stuck at fault models, scan design, BIST and IDDQ testing?

Intel,

3 12037

What is SPICE?

Intel,

4 15725

Differences between IRSIM and SPICE?

Intel,

4937

Differences between netlist of HSPICE and Spectre?

Intel,

1 7973

What is FPGA?

Intel,

7 12336

Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

Intel,

2845

Draw the Layout of an Inverter?

Intel,

2033

If the current thru the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

Intel,

1 6051

Implement F = AB+C using CMOS gates?

Intel,

2 10056

Working of a 2-stage OPAMP?

Intel, Tata Elxsi,

2595


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Un-Answered Questions { VLSI }

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

774


In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

571


Explain Cross section of an NMOS transistor?

558


Explain Basic Stuff related to Perl?

599


Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

626






In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

3583


How does Vbe and Ic change with temperature?

2943


Explain the working of 4-bit Up/down Counter?

3976


How do you size NMOS and PMOS transistors to increase the threshold voltage?

2526


What is the purpose of having depletion mode device?

606


Explain the three regions of operation of a mosfet.

616


If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

2002


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3377


What are the different design constraints occur in the synthesis phase?

677


What does it mean “the channel is pinched off”?

839