Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
626Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
887In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
676Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
684Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
709Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
681
what is a sequential circuit?
If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
Draw the SRAM Write Circuitry
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
Explain the Working of a 2-stage OPAMP?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
What are the different design constraints occur in the synthesis phase?
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
How does Vbe and Ic change with temperature?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
why is the number of gate inputs to CMOS gates usually limited to four?
What types of high speed CMOS circuits have you designed?
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
What are the different gates where boolean logic are applicable?
