Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
1069Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
1321In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
1139Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
1158Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
1164Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
1093Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
1100
What types of CMOS memories have you designed? What were their size? Speed?
What is the function of enhancement mode transistor?
What transistor level design tools are you proficient with? What types of designs were they used on?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What is the ideal input and output resistance of a current source?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
What is the main function of metastability in vsdl?
Give various factors on which threshold voltage depends.
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
What happens if we delay the enabling of Clock signal?
What are the different gates where boolean logic are applicable?
What was your role in the silicon evaluation or product ramp? What tools did you use?
If not into production, how far did you follow the design and why did not you see it into production?
How binary number can give a signal or convert into a digital signal?
6-T XOR gate?