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There are 2 Flip_Flop with logic between them. Given Clock
to Q delay, logic prop. delay, set up and hold times specify
maximum clock frequency of system.
What happens if second output fed back to first input. Any
changes? What happens with timing if second output is fed
back to logic between the flops? Good Luck!
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Answer / guest
This is related setup and hold time violations. Answer is:
Tc-q + Tsetup + Tcskew + Tcomb <= T period (setup)
Tc-q + Tcomb - Tcskew >= Thold (holdtime)
Short path -> possible hold time violation.
Long path -> possible set up time violation.
| Is This Answer Correct ? | 9 Yes | 6 No |
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