Answer / puli

latch up is the condition in which parasitic elements
establish a low impedance path between vdd and vss resulting
undesirable effects.



use guard rings or use well,substrate taps to prevent the
latch up

Answer / pawan hegde

1.GUARD RING , 2.Appropriate TAPS, 3.MAINTAIN WELL
PROXIMITY , 4 .Use Triple Well process , 5.Dual well
process 6 ???

What is component binding?

2 Answers   Intel,

---

Mention what are three regions of operation of mosfet and how are they used?

0 Answers  

---

What are the different gates where boolean logic are applicable?

0 Answers  

---

Explain what is multiplexer?

0 Answers  

---

What are the main issues associated with multiprocessor caches and how might you solve them?

0 Answers   Intel,

---

what is Early effects and their physical origin.

1 Answers  

---

Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  

---

what is conductance and valence band?

1 Answers  

---

Explain Cross section of a PMOS transistor?

0 Answers   Intel,

---

What is a linked list? Explain the 2 fields in a linked list?

1 Answers   Intel,

---

what is body effect?

1 Answers  

---

Implement F = AB+C using CMOS gates?

2 Answers   Intel,

---