Answer / baba

Dynamic CMOS ckts and high speed multipliers using
BOOTh/Mod-Booth algorithm.

Answer / narasimha reddy d l

generally the static circuits will occupy more space but
the dynamic circuit contains only one pmos device it
occupies less space and the power dessipation and delay are
reduced to get high performance. still we use domino
circuits which contains an additional not gate at the
output to avoiding the cascading problem in dynamic
circuits. this offers more ferformance by increasing the
noise immunity.

what is the difference between the testing and verification?

1 Answers   Intel,

---

Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,

---

What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?

4 Answers   Intel,

---

Explain the three regions of operation of a mosfet.

0 Answers  

---

Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

0 Answers   Intel,

---

Are you familiar with the term snooping?

0 Answers   Intel,

---

What?s the difference between Testing & Verification?

6 Answers   Infosys,

---

What happens to delay if you increase load capacitance?

3 Answers   Infosys,

---

Implement F = AB+C using CMOS gates?

2 Answers   Intel,

---

Factors affecting Power Consumption on a chip?

7 Answers   Intel,

---

Mention what are the different gates where Boolean logic are applicable?

0 Answers  

---

Insights of a 2 input NOR gate. Explain the working?

1 Answers   Infosys, Intel,

---