How can you construct both PMOS and NMOS on a single substrate?

0 Answers   IBM, Intel,

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Explain the operation of a 6T-SRAM cell?

0 Answers   Intel,

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Insights of a Tri-State Inverter?

3 Answers   Intel,

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Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

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what is charge sharing?

0 Answers   Intel,

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Draw the stick diagram of a NOR gate. Optimize it

0 Answers   Infosys,

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Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

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Explain what is the use of defpararm?

0 Answers  

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What is SPICE?

4 Answers   Intel,

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Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

2 Answers   Infosys,

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Explain the various Capacitances associated with a transistor and which one of them is the most prominent?

2 Answers   Intel,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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