Describe a finite state machine that will detect three
consecutive coin tosses (of one coin) that results in
heads.
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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
What is Fowler-Nordheim Tunneling?
Why don?t we use just one NMOS or PMOS transistor as a transmission gate?
What are the different design constraints occur in the synthesis phase?
What types of high speed CMOS circuits have you designed?
What is a D-latch? Write the VHDL Code for it?
Have you studied buses? What types?
Explain the difference between write through and write back cache.
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
Draw the stick diagram of a NOR gate. Optimize it
What are set up time & hold time constraints? What do they signify?
How can you model a SRAM at RTL Level?