Answer / lu

Charge sharing is an undesirable signal integrity phenomenon
observed most commonly in the domino logic family of digital
circuits. The charge sharing problem occurs when the charge
which is stored at the output node in the phase is shared
among the output or junction capacitance of transistors
which are in the evaluation phase. Charge sharing may
degrade the output voltage level or even cause erroneous
output value

Answer / gk

it is like suppose you have two capacitors connected in series/parallel there will be charge sharing. in mosfet we want the gate capacitance to control channel only.but gate to drain overlapping(coupling) at the end of channel creates capacitance(Cgd) similarly at source also. there is PN junction depletion capacitance at drain/source with substrate completes path. This path creates coupling of input to drain.

what is Channel length modulation?

2 Answers   Intel,

---

Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

0 Answers   Infosys,

---

Draw the SRAM Write Circuitry

0 Answers   Infosys,

---

In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

---

How about voltage source?

0 Answers  

---

Explain what is slack?

0 Answers  

---

For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

---

Are you familiar with the term snooping?

0 Answers   Intel,

---

Explain the three regions of operation of a mosfet.

0 Answers  

---

Why do we use a Clock tree?

3 Answers   Intel,

---

Are you familiar with VHDL and/or Verilog?

1 Answers   Intel,

---

Differences between DRAM and SRAM?

14 Answers   Infosys, Intel, University, Wipro,

---