Answer / lu

Charge sharing is an undesirable signal integrity phenomenon
observed most commonly in the domino logic family of digital
circuits. The charge sharing problem occurs when the charge
which is stored at the output node in the phase is shared
among the output or junction capacitance of transistors
which are in the evaluation phase. Charge sharing may
degrade the output voltage level or even cause erroneous
output value

Answer / gk

it is like suppose you have two capacitors connected in series/parallel there will be charge sharing. in mosfet we want the gate capacitance to control channel only.but gate to drain overlapping(coupling) at the end of channel creates capacitance(Cgd) similarly at source also. there is PN junction depletion capacitance at drain/source with substrate completes path. This path creates coupling of input to drain.

Explain ASIC Design Flow?

2 Answers   Intel, JK Associates, Mind Tree,

---

Insights of a Tri-state inverter?

1 Answers   Intel,

---

What was your role in the silicon evaluation or product ramp? What tools did you use?

0 Answers   Intel,

---

What are the Factors affecting Power Consumption on a chip?

0 Answers   Intel,

---

What are the different classification of the timing control?

0 Answers  

---

What is a D-latch? Write the VHDL Code for it?

3 Answers   Intel,

---

6-T XOR gate?

0 Answers   Intel,

---

What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,

---

What does it mean “the channel is pinched off”?

0 Answers  

---

In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

---

What is FPGA?

7 Answers   Intel,

---

Mention what are the different gates where Boolean logic are applicable?

0 Answers  

---