Answer / shashank agarwal

Since delay=f*C*Vdd^2, delay increases with the increase in the load capacitance

What happens if we use an Inverter instead of the Differential Sense Amplifier?

0 Answers  

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Cross section of an NMOS transistor?

3 Answers   Intel,

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What is the difference between fifo and the memory?

6 Answers   DewSoft, Intel, Pentagon Rugged Systems,

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

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If the current thru the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

1 Answers   Intel,

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What is Noise Margin? Explain the procedure to determine Noise Margin?

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Implement F= not (AB+CD) using CMOS gates?

1 Answers   Intel,

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Explain the Various steps in Synthesis?

0 Answers   Intel,

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What was your role in the silicon evaluation or product ramp? What tools did you use?

0 Answers   Intel,

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Implement an Inverter using a single transistor?

4 Answers   Intel,

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How binary number can give a signal or convert into a digital signal?

0 Answers  

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Explain depletion region.

0 Answers  

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