Answer / shashank agarwal

Since delay=f*C*Vdd^2, delay increases with the increase in the load capacitance

What?s the difference between Testing & Verification?

6 Answers   Infosys,

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What is the function of chain reordering?

0 Answers  

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How do you size NMOS and PMOS transistors to increase the threshold voltage?

4 Answers  

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What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

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Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,

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You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

0 Answers   Intel,

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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What is hot electron effect?

3 Answers   Intel,

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In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

0 Answers  

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For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?

5 Answers   Intel,

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Basic Stuff related to Perl?

0 Answers   Intel,

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Working of a 2-stage OPAMP?

0 Answers   Intel, Tata Elxsi,

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