What is latchup? Explain the methods used to prevent it?
Answer Posted / puli
latch up is the condition in which parasitic elements
establish a low impedance path between vdd and vss resulting
undesirable effects.
use guard rings or use well,substrate taps to prevent the
latch up
| Is This Answer Correct ? | 16 Yes | 1 No |
Post New Answer View All Answers
What are the steps required to solve setup and hold violations in vlsi?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
What was your role in the silicon evaluation/product ramp? What tools did you use?
what is the use of defpararm?
If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
What are the Factors affecting Power Consumption on a chip?
What products have you designed which have entered high volume production?
Working of a 2-stage OPAMP?
what is multiplexer?
Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
What types of CMOS memories have you designed? What were their size? Speed?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?