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What are the limitations in increasing the power supply to
reduce delay?

Answers were Sorted based on User's Feedback



What are the limitations in increasing the power supply to reduce delay?..

Answer / arpan

increasing vdd increeases power dissipation as

switching power = c vdd**2 f

also at submicron level , increasing vdd amy lead to hgh
feild in the device....leading to its failure

Is This Answer Correct ?    10 Yes 0 No

What are the limitations in increasing the power supply to reduce delay?..

Answer / narasimha reddy d l

power supply is directly praportional to the sub-micron
leakage current so if Vdd increases the leakage current
will increases

Is This Answer Correct ?    1 Yes 2 No

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