What are the limitations in increasing the power supply to
reduce delay?
Answers were Sorted based on User's Feedback
Answer / arpan
increasing vdd increeases power dissipation as
switching power = c vdd**2 f
also at submicron level , increasing vdd amy lead to hgh
feild in the device....leading to its failure
| Is This Answer Correct ? | 10 Yes | 0 No |
Answer / narasimha reddy d l
power supply is directly praportional to the sub-micron
leakage current so if Vdd increases the leakage current
will increases
| Is This Answer Correct ? | 1 Yes | 2 No |
Insights of a Tri-state inverter?
Mention what are the two types of procedural blocks in Verilog?
Explain the various MOSFET Capacitances & their significance ?
Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)
Explain what is multiplexer?
Give the various techniques you know to minimize power consumption?
What is the build-in potential?
Explain what is the use of defpararm?
Explain about stuck at fault models, scan design, BIST and IDDQ testing?
What happens to delay if you increase load capacitance?
Are you familiar with the term MESI?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.