Answer / refedo

1. Verilog is based on C, while VHDL is based on Pascal and Ada.

2. Unlike Verilog, VHDL is strongly typed.

3. Ulike VHDL, Verilog is case sensitive.

4. Verilog is easier to learn compared to VHDL.

5. Verilog has very simple data types, while VHDL allows
users to create more complex data types.

6. Verilog lacks the library management, like that of VHDL.

Read more: Difference Between Verilog and VHDL | Difference
Between
http://www.differencebetween.net/technology/difference-between-verilog-and-vhdl/#ixzz0ti9ocWih

Answer / suraj thakur

verilog is use in mobile fabrication and VHDL is use in
digital ckt fabrication.

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