Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...


Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency of
an instruction in a 5 stage machine? What is the throughput
of this machine ?

Answers were Sorted based on User's Feedback



Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, w..

Answer / mallikarjun patil

I have worked on design consit of 5 stage pipeline
processor.

With 5 stage pipeline it takes minimum 5 clock cycle to to
execute a instuction. So latency of instuction is5 clock
cycles.

Through put is one instruction per clock cycle + initial
overhed of 4 clock cycle

Is This Answer Correct ?    27 Yes 3 No

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, w..

Answer / 12345678

1.Instruction fetch
2.decode instruction and read register files
3.execute
4.data to access from memory
5.write back

throughput is the total amount of work done in a given time,

Is This Answer Correct ?    21 Yes 9 No

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, w..

Answer / kiran chowdary

Throughput is 1 instruction/clock cycle. It is a dumb answer to say the latency as 5 cycles. It is pipelined architecture. Only during initial time it takes 5 cycles to fetch and all that. Later on all executions are pipelined so it takes only 1 cycle to execute one instruction unless there is any blocking activity like memory write back etc.

Is This Answer Correct ?    6 Yes 8 No

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, w..

Answer / manju

the steps are same as mentioned in the above thread jus
putting these in proper order.
1.Instruction fetch
2.decode instruction and read register files
3.data to access from memory
4.execute
5.write back

please correct if it is wrong.

Is This Answer Correct ?    1 Yes 12 No

Post New Answer

More VLSI Interview Questions

What is the difference between nmos and pmos technologies?

0 Answers  


Differences between netlist of HSPICE and Spectre?

1 Answers   Intel,


Have you studied buses? What types?

1 Answers   Intel,


What are the various regions of operation of mosfet? How are those regions used?

0 Answers  


What are the total number of lines written by you in C/C++? What compiler was used?

1 Answers   Intel, Zensar,


Describe the various effects of scaling?

0 Answers   Infosys,


What happens to delay if you increase load capacitance?

3 Answers   Infosys,


What are the steps required to solve setup and hold violations in vlsi?

0 Answers  


Explain the Charge Sharing problem while sampling data from a Bus?

0 Answers  


Implement a function with both ratioes and domino logic and merits and demerits of each logic?

0 Answers   Intel,


Implement a function with both ratioed and domino logic and merits and demerits of each logic?

0 Answers   Intel,


What is the main function of metastability in vsdl?

0 Answers  


Categories