Answer / mallikarjun patil

I have worked on design consit of 5 stage pipeline
processor.

With 5 stage pipeline it takes minimum 5 clock cycle to to
execute a instuction. So latency of instuction is5 clock
cycles.

Through put is one instruction per clock cycle + initial
overhed of 4 clock cycle

Answer / 12345678

1.Instruction fetch
2.decode instruction and read register files
3.execute
4.data to access from memory
5.write back

throughput is the total amount of work done in a given time,

Answer / kiran chowdary

Throughput is 1 instruction/clock cycle. It is a dumb answer to say the latency as 5 cycles. It is pipelined architecture. Only during initial time it takes 5 cycles to fetch and all that. Later on all executions are pipelined so it takes only 1 cycle to execute one instruction unless there is any blocking activity like memory write back etc.

Answer / manju

the steps are same as mentioned in the above thread jus
putting these in proper order.
1.Instruction fetch
2.decode instruction and read register files
3.data to access from memory
4.execute
5.write back

please correct if it is wrong.

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