What are the steps involved in preventing the metastability?

0 Answers  

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What are the steps involved in designing an optimal pad ring?

0 Answers  

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Implement a 2 I/P and gate using Tran gates?

0 Answers   Intel,

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what is multiplexer?

0 Answers  

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Advantages and disadvantages of Mealy and Moore?

2 Answers   Intel,

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What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

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Explain the difference between write through and write back cache.

2 Answers   Intel,

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What is Body Effect?

0 Answers   CG CoreEL, Cisco, TA,

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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

0 Answers   Infosys,

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Factors affecting Power Consumption on a chip?

7 Answers   Intel,

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In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

1 Answers   Intel,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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