In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
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What is the depletion region?
Id vs. Vds Characteristics of NMOS and PMOS transistors?
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Explain the working of Insights of a pass gate ?
Explain about stuck at fault models, scan design, BIST and IDDQ testing?
what is the difference between the TTL chips and CMOS chips?
What happens if we delay the enabling of Clock signal?
Implement a 2 I/P and gate using Tran gates?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
What are the changes that are provided to meet design power targets?
What are the various regions of operation of mosfet? How are those regions used?
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?