Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

0 Answers   Infosys,

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What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

0 Answers   Intel,

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Explain sizing of the inverter?

0 Answers   Infosys,

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

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Cross section of a PMOS transistor?

0 Answers   Intel,

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What is the difference between the mealy and moore state machine?

0 Answers  

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Explain the Working of a 2-stage OPAMP?

0 Answers   Intel,

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In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

0 Answers  

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Explain why present VLSI circuits use MOSFETs instead of BJTs?

0 Answers  

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What was your role in the silicon evaluation/product ramp? What tools did you use?

0 Answers   Intel,

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Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

2 Answers   Infosys,

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Draw a CMOS Inverter. Explain its transfer characteristics

0 Answers   Infosys,

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