Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...


What is Fowler-Nordheim Tunneling?

Answers were Sorted based on User's Feedback



What is Fowler-Nordheim Tunneling?..

Answer / nikki

This is a phenomena associated with the gate thickness of a
transistor. When the thickness of oxide is very small there
exists a possibilty that electrons pass directly between
source and gate. This is a seond order effect and limits
the scaling down of transistor size.

Is This Answer Correct ?    8 Yes 0 No

What is Fowler-Nordheim Tunneling?..

Answer / bob

FN Tunneling is only a second order effect, unless you are
desiging Flash memory. In which case, the FN tunneling is
the first order mechanism for programming and erasing the
memory cell.

Is This Answer Correct ?    4 Yes 0 No

Post New Answer

More VLSI Interview Questions

How do you size NMOS and PMOS transistors to increase the threshold voltage?

0 Answers   Infosys,


Draw a CMOS Inverter. Explain its transfer characteristics

0 Answers   Infosys,


What is the function of enhancement mode transistor?

0 Answers  


Different ways of implementing a comparator?

1 Answers   Intel,


Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

0 Answers   Infosys,


Explain the Working of a 2-stage OPAMP?

0 Answers   Intel,


Explain about 6-T XOR gate?

0 Answers   Intel,


What are the different design constraints occur in the synthesis phase?

0 Answers  


For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

0 Answers   Infosys,


What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,


What is the difference between nmos and pmos technologies?

0 Answers  


Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  


Categories