Answer / nikki

Post layout extraction is neccessary to get the accurate
netlist , with parasitic capacitance and rasistance. Post
layout simulation are done using the extracted neltist as
this gives a better approximation of what the circuit
behaviour would be in silicon.

What is clock feed through?

2 Answers   Intel,

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How do you detect if two 8-bit signals are same?

6 Answers  

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What is the difference between fifo and the memory?

6 Answers   DewSoft, Intel, Pentagon Rugged Systems,

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Give the expression for CMOS switching power dissipation?

2 Answers   Cypress Semiconductor,

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what is Early effects and their physical origin.

1 Answers  

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What are the two types of noise of MOSFET, how to eliminate them?(Thermal and Flicker).

4 Answers   Analog Devices,

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0 Answers   Intel,

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1 Answers   IIT, Intel,

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Write a VLSI program that implements a toll booth controller?

0 Answers   Patni,

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What is the difference between = and == in C?

5 Answers   Intel,

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In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

0 Answers  

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A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?

3 Answers   Intel,

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