Answer / nikki

Post layout extraction is neccessary to get the accurate
netlist , with parasitic capacitance and rasistance. Post
layout simulation are done using the extracted neltist as
this gives a better approximation of what the circuit
behaviour would be in silicon.

Give the cross-sectional diagram of the cmos.

0 Answers  

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Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

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Explain Cross section of an NMOS transistor?

0 Answers   Intel,

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Define threshold voltage?

32 Answers   College School Exams Tests, Intel, JHG, Wipro,

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Explain the usage of the shared SPI bus?

1 Answers  

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Working of a 2-stage OPAMP?

0 Answers   Intel, Tata Elxsi,

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Explain the operation considering a two processor computer system with a cache for each processor.

0 Answers   Intel,

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Explain why present VLSI circuits use MOSFETs instead of BJTs?

0 Answers  

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Explain what is scr (silicon controlled rectifier)?

0 Answers  

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verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.

2 Answers   Cosmic Circuits, HP,

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What does the above code synthesize to?

0 Answers   Intel,

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what is verilog?

0 Answers  

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