Answer / nikki

Post layout extraction is neccessary to get the accurate
netlist , with parasitic capacitance and rasistance. Post
layout simulation are done using the extracted neltist as
this gives a better approximation of what the circuit
behaviour would be in silicon.

what is the difference between the testing and verification?

1 Answers   Intel,

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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

0 Answers   Infosys,

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What are the limitations in increasing the power supply to reduce delay?

2 Answers   Infosys,

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Give the various techniques you know to minimize power consumption?

5 Answers  

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How about voltage source?

0 Answers  

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Implement F = AB+C using CMOS gates?

2 Answers   Intel,

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Insights of a 4bit adder/Sub Circuit?

0 Answers   Intel,

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Explain what is Verilog?

0 Answers  

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Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,

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Explain about 6-T XOR gate?

0 Answers   Intel,

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Are you familiar with VHDL and/or Verilog?

1 Answers   Intel,

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Draw the stick diagram of a NOR gate. Optimize it

0 Answers   Infosys,

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