Answer / nikki

Post layout extraction is neccessary to get the accurate
netlist , with parasitic capacitance and rasistance. Post
layout simulation are done using the extracted neltist as
this gives a better approximation of what the circuit
behaviour would be in silicon.

What is the difference between synchronous and asynchronous reset?

0 Answers  

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What products have you designed which have entered high volume production?

1 Answers   Intel,

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If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

0 Answers   Intel,

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Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,

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What is a D-latch? Write the VHDL Code for it?

3 Answers   Intel,

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What does the above code synthesize to?

0 Answers   Intel,

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Give the expression for CMOS switching power dissipation?

2 Answers   Infosys,

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For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

0 Answers   Infosys,

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Mention what are the two types of procedural blocks in Verilog?

0 Answers  

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What is component binding?

2 Answers   Intel,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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What's the price in 1K quantity?

0 Answers   Wipro,

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