Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...


What is clock feed through?

Answers were Sorted based on User's Feedback



What is clock feed through?..

Answer / sunil b r

he accumulation of a small positive charge on the source of
a MOS switch which occurs after the switch has been turned
off due to the parasitic capacitance that exists between the
gate and the source of the transistor, known as clock
feedthrough, is reduced by utilizing a split-gate MOS
transistor, and by continuously biasing one of the gates of
the split-gate transistor.

Is This Answer Correct ?    25 Yes 3 No

What is clock feed through?..

Answer / sudeep

Assume u have 2-3 partitions in ur design and now if the
clk for the second partition hs to go thru the first
partition, then the tool doesnt know which is the source or
root pin of the clk for the second partition, then u need
to specify the clock as a "feed thru" clock in the first
partition !

Is This Answer Correct ?    9 Yes 15 No

Post New Answer

More VLSI Interview Questions

Working of a 2-stage OPAMP?

0 Answers   Intel, Tata Elxsi,


Differences between blocking and Non-blocking statements in Verilog?

5 Answers   Intel,


What products have you designed which have entered high volume production?

0 Answers   Intel,


Explain CMOS Inverter transfer characteristics?

0 Answers   ADS,


What happens if we delay the enabling of Clock signal?

0 Answers  


Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  


what is the doping?

5 Answers  


You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,


What are the Factors affecting Power Consumption on a chip?

0 Answers   Intel,


Give the expression for calculating Delay in CMOS circuit?

1 Answers   Infosys,


What happens to delay if you increase load capacitance?

1 Answers   Google,


what is conductance and valence band?

1 Answers  


Categories