You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,

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What are the changes that are provided to meet design power targets?

0 Answers  

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what is verilog?

0 Answers  

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Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

3 Answers   Intel,

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What is setup time and hold time?

1 Answers   Intel,

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For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

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What is validation?

2 Answers   Intel,

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How can you model a SRAM at RTL Level?

0 Answers   Infosys,

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What happens when the gate oxide is very thin?

3 Answers   Intel,

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Explain the working of differential sense amplifier?

1 Answers  

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What is Body Effect?

0 Answers   CG CoreEL, Cisco, TA,

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What is the function of enhancement mode transistor?

0 Answers  

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