What are the steps involved in designing an optimal pad ring?
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In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
For CMOS logic, give the various techniques you know to minimize power consumption
what is verilog?
What products have you designed which have entered high volume production?
Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
What is the difference between synchronous and asynchronous reset?
What are the main issues associated with multiprocessor caches and how might you solve them?
How do you detect if two 8-bit signals are same?
Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)
Explain the operation of a 6T-SRAM cell?
Different ways of implementing a comparator?