What was your role in the silicon evaluation/product ramp?
What tools did you use?
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what is verilog?
Factors affecting Power Consumption on a chip?
Why do we use a Clock tree?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
How to find the read failiure probablity in SRAM?
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
what is the difference between the testing and verification?
Insights of a 4bit adder/Sub Circuit?
Explain Custom Design Flow?
What is the difference between nmos and pmos technologies?
What's the price in 1K quantity?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?