Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

0 Answers   Infosys,

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what is verilog?

0 Answers  

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Give the expression for CMOS switching power dissipation?

2 Answers   Infosys,

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What happens to delay if you increase load capacitance?

3 Answers   Infosys,

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,

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For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

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Tell me how MOSFET works.

0 Answers  

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what are three regions of operation of MOSFET and how are they used?

0 Answers  

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What is threshold voltage?

0 Answers  

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Explain how Verilog is different to normal programming language?

0 Answers  

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Differences between functions and Procedures in VHDL?

5 Answers   Intel,

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What was your role in the silicon evaluation/product ramp? What tools did you use?

0 Answers   Intel,

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