Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

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What is Fermi level?

5 Answers  

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In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

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For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

3 Answers   Intel,

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Cross section of an NMOS transistor?

3 Answers   Intel,

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What is charge sharing?

2 Answers   Cypress Semiconductor, Intel,

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What products have you designed which have entered high volume production?

0 Answers   Intel,

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What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

0 Answers   Infosys,

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What is the depletion region?

1 Answers  

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Explain CMOS Inverter transfer characteristics?

0 Answers   ADS,

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Explain the operation of a 6T-SRAM cell?

0 Answers   Intel,

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