Answer / hasan

help for pipeline circuit simulation code by HSPICE.

Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

2 Answers   Infosys,

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Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

3 Answers   Intel,

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

0 Answers   Infosys,

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Differences between Array and Booth Multipliers?

0 Answers   Intel,

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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Explain about 6-T XOR gate?

0 Answers   Intel,

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What are the changes that are provided to meet design power targets?

0 Answers  

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What is the difference between synchronous and asynchronous reset?

0 Answers  

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What are the different limitations in increasing the power supply to reduce delay?

2 Answers  

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Tell me the parameters as many as possible you know that used to character an amplifier?

1 Answers  

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Differences between D-Latch and D flip-flop?

17 Answers   AIT, Intel, Sibridge Technologies,

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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,

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