Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

1 Answers   IIT, Intel,

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Draw a CMOS Inverter. Explain its transfer characteristics

0 Answers   Infosys,

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Give the expression for CMOS switching power dissipation?

2 Answers   Infosys,

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For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

3 Answers   Intel,

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Tell me the parameters as many as possible you know that used to character an amplifier?

1 Answers  

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In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

1 Answers   Intel,

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What is the difference between synchronous and asynchronous reset?

0 Answers  

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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

0 Answers   Infosys,

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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What are the Advantages and disadvantages of Mealy and Moore?

0 Answers   Intel,

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Explain the various Capacitances associated with a transistor and which one of them is the most prominent?

2 Answers   Intel,

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