Interested to Buy Any Domain ? << Click Here >> for more details...
Answer Posted / sudeep
Assume u have 2-3 partitions in ur design and now if the
clk for the second partition hs to go thru the first
partition, then the tool doesnt know which is the source or
root pin of the clk for the second partition, then u need
to specify the clock as a "feed thru" clock in the first
partition !
| Is This Answer Correct ? | 9 Yes | 15 No |
Post New Answer View All Answers
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
What products have you designed which have entered high volume production?
Design an 8 is to 3 encoder using 4 is to encoder?
Draw a 6-T SRAM Cell and explain the Read and Write operations
What are the Factors affecting Power Consumption on a chip?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
How does Vbe and Ic change with temperature?
What are the different gates where boolean logic are applicable?
Are you familiar with the term MESI?
What was your role in the silicon evaluation or product ramp? What tools did you use?
What does the above code synthesize to?
Draw a CMOS Inverter. Explain its transfer characteristics
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
Give various factors on which threshold voltage depends.
